DFT Intern

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams, contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations), and develop flows for various ATPG fault models. You do not necessarily need prior DFT experience; just the ability to learn quickly in a fast-paced, high-autonomy environment. We are looking for Summer '26, Fall '26, Spring '27, and Summer '27 interns.

You may be a good fit if you have

- Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.

- Familiarity with a hardware description language (Verilog or SystemVerilog)

- Exposure to ASIC or SoC design concepts

- Familiarity with digital logic design fundamentals

- Familiarity with standard ASIC design flow steps (synthesis, STA, DFT)

- Familiarity with scripting in Python, Tcl, or another language

- Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Strong candidates may also have experience with

- Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression

- Experience with Tessent or similar DFT tooling

- Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF)

- Exposure to DFT flow automation or regression infrastructure

- Familiarity with clocking and reset schemes

We encourage you to apply even if you do not believe you meet eve...