Formal Verification - DV
About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
We are seeking a Formal Verification Engineer to join our ASIC Design Verification team. You will drive formal verification across the custom IP, interface IP, and SoC subsystems that power our ASICs, including compute arrays, DMA engines, NoCs, memory systems, PCIe, Ethernet, CPU subsystems, low-power peripherals, and vendor IP wrappers. You will work closely with architects, RTL designers, DV engineers, emulation teams, and software/firmware teams to prove design correctness, expose deep corner-case bugs, and improve verification closure across the full chip.
Key Responsibilities
- Define and drive formal verification strategy across the ASIC DV team for complex IP blocks, interface subsystems, and SoC integration logic.
- Develop formal verification plans covering functional correctness, connectivity, ordering, reset behavior, configuration legality, and deadlock/livelock freedom.
- Build reusable formal environments using SystemVerilog Assertions, assumptions, constraints, checkers, cut-points, abstraction models, and reference models.
- Drive proof convergence using abstractions, cut-points, assume-guarantee reasoning, cover properties, bounded-proof analysis, and coverage metrics to establish formal sign-off confidence.
- Work with architects and RTL designers to translate design intent and specifications into high-value formal properties and closure criteria.
- Partner with UVM DV, emulation, software, and firmware teams to align formal verification with simulation, coverage, regressions...