Senior Principal Digital Design Engineer
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.Role OverviewAstera Labs is seeking a Senior Principal Digital Design Engineer to drive the architecture and implementation of next-generation digital designs powering AI infrastructure connectivity. This is a high-impact technical leadership role where you'll define micro-architecture strategies for better power, performance and area tradeoff, own complex chip-level design decisions, and guide multiple blocks from concept through silicon bring-up for industry-leading products supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. As a senior technical leader, you'll shape design methodologies, mentor engineering teams, and collaborate cross-functionally with verification, physical design, DFT, and post-silicon teams to deliver high-performance, production-quality silicon. You'll also influence roadmap decisions and drive design excellence across the organization, ensuring Astera Labs continues to set the standard for AI connectivity solutions. Key Responsibilities Architecture & Technical Leadership Define and drive micro-architecture for complex digital blocks and subsystems across multiple product lines Establish architectural standards and best practices that scale across the design organization Provide technical guidance and decision-making on critical design trade-offs impacting performance, power, and area Design Execution & Ownership Lead RTL implementation of complex designs from architecture definition through GDS and silicon bring-up Drive timing constraints and closure strategies and implement robust Design-for-Test (DFT) methodologies Own accountability for design quality, schedule, and successful production delivery Cross-Functional Collaboration Partner with verification teams to develop comprehensive test plans, achieve coverage closure, and debug complex issues Collaborate with physical design, DFT, and post-silicon teams to ensure seamless integration and bring-up Work with firmware and software teams to optimize hardware-software interfaces Mentorship & Process Excellence Mentor and develop junior and senior engineers, elevating team technical capabilities Drive continuous improvement of silicon development processes, CAD autom...