Senior Principal Engineer, Hardware Application Engineering — Signal Integrity & Power Integrity
Key Responsibilities Serve as the senior SI/PI technical authority for customer platforms built on Ethernet switches and UALink silicon, from early channel definition through mass-production qualification. Define and maintain layout and routing guidelines for high-speed SerDes channels, power delivery networks, and sensitive analog interfaces — and drive their adoption with customers, ODMs, and internal teams. Perform post-silicon channel extraction, full-channel simulation, and what-if analysis on customer board designs, and recommend targeted layout and stack-up fixes that move designs from "passing" to "best-in-class margins. Lead compliance testing and lab characterization — BER/SER, eye-opening margins, jitter, return loss, crosstalk — and translate measurement data into actionable design and SerDes-tuning guidance. Provide SerDes tuning guidance to customers based on simulation results, lab measurements, and field telemetry; partner with silicon teams to refine tuning methodologies. Run and review power integrity simulations covering PDN impedance, IR drop, decoupling effectiveness, transient response, and droop, and guide customers on robust PDN architectures for high-current ASICs. Translate customer power needs and constraints into structured feedback for silicon, packaging, and platform engineering teams — closing the loop for continuous product improvement. Engage directly with ODMs on SI/PI guidance, design reviews, and qualification activities, partnering with the global Customer Solutions Group and internal engineering teams. Support definition and validation of reference designs for new silicon — owning the SI/PI side of the design from early channel budgeting through customer release. Provide hands-on lab debug expertise during customer bring-up and production ramp, using VNAs, BERTs, real-time scopes, TDR equipment, jitter analyzers, and compliance test kits. Develop and deliver SI/PI training to customers, ODMs, and internal teams — covering high-speed design best practices, simulation methodology, and lab debug techniques. Provide technical leadership on 112G and 224G PAM4 SerDes designs today, and help shape SI/PI approach for next-generation 448G systems. Partner closely with Silicon Design, Packaging, Board/System HW, Software, and Operations teams to deliver fully integrated solutions. Contribute to product definition and roadmap planning by bringing real-world SI/PI insights into architecture and marketing discussions.What We're Looking ForPhD, Master's, or Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.15+ years of experience in hardware design, development, and validation of high-speed networking or compute systems.10+ years of focused experience in signal integrity and power integrity work on high-speed SerDes platforms (25G NRZ through 112G/224G PAM4).Demonstrated expertise across the full SI lifecycle: channel modeling and budgeting, layout and stack-up guideline definition, p...