Sr. Principal Product Engineer, Silicon Signoff Verification (SSV) / Digital Implementation & Signoff Solutions

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.We are seeking a Senior Principal Product Engineer (8-12+ years industry experience) to lead advanced signoff methodology development, customer enablement, and product deployment activities for Cadence's timing signoff and ECO solutions. The ideal candidate will possess deep expertise in STA, MMMC signoff, ECO convergence, power optimization, signal integrity, and physical implementation, along with strong customer-facing skills and the ability to influence product direction through close collaboration with R&D and strategic semiconductor customers. Key ResponsibilitiesDrive development and deployment of advanced signoff methodologies covering timing, power, signal integrity, and ECO closure.Collaborate with customers, AE teams, and R&D to resolve complex design closure challenges.Lead qualification and certification activities for advanced-node design flows.Develop and optimize multi-mode multi-corner (MMMC) timing closure methodologies.Drive signoff correlation across implementation, STA, SPICE, and signoff environments.Define and validate methodologies for: Setup and hold closurePower optimizationCrosstalk mitigationGlitch fixingMax transition and electrical rule fixingMulti-view timing closureSupport customer tapeouts and critical project milestones through root-cause analysis and debug.Partner with R&D to prioritize and validate product enhancements and customer-driven requirements.Create deployment collateral, technical presentations, and best-practice methodologies.Drive adoption of emerging technologies including AI-assisted signoff and ECO automation. Required Technical SkillsStrong expertise in Static Timing Analysis (STA)Multi-mode multi-corner (MMMC) timing analysisSignoff methodologies and timing convergenceStatistical timing analysisSignal Integrity and Crosstalk AnalysisGlitch analysis and fixing methodologiesECO implementation and closure flowsTiming correlation and SPICE correlationPower optimization techniquesBoundary model and hierarchical timing flowsRC extraction and parasitic analysisPhysical implementation and signoff optimization Desired Tool ExperienceCadence Tempus/PrimeTimeCadence Innovus/ICC/FCTempus ECO/TweakerPhysical implementation and signoff environmentsAI-assisted design closure workflows Preferred Industry ExperienceAdvanced-node ASIC or SoC developmentFoundry qualification and certification programsCustomer-facing product engineeringLarge-scale semiconductor design closureTiming, power, and SI signoff methodologies Leadership ExpectationsServe as technical lead for strategic customer engagements.Influence product roadmap and methodology direction.Mentor engineers and drive cross-functional collaboration.Lead technical reviews and customer escalation management. Required Experience8-12+ years of industry experience in semiconductor design, physical implementati...