D Matrix

Sr. Staff PCB Design Engineer

Santa Clara, Ca, California, United StatesFull timeStaff$175,000 - $265,000 / yearPosted 7 days ago
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At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.

We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI.

Role Overview

As Sr. Staff PCB Design Engineer, you will lead the physical design of the boards that connect d-Matrix's AI silicon to the world. Our "Corsair" platforms push the limits of signal density and power delivery, and you will own layout for high-complexity, high-layer-count PCBAs (20+ layers) — ensuring 112G/224G SerDes signals stay clean and thousands of amps are delivered with minimal loss. Beyond hands-on layout, you will serve as custodian of our Design Methodology, driving the automation, tooling, and constraint management processes that let hardware development scale with precision and speed. You'll partner closely with power, ASIC, and manufacturing teams, and have the autonomy to build layout infrastructure from the ground up.

What You Will Do

  • Lead full-cycle layout for high-complexity AI accelerator cards (PCIe form factors) and system baseboards
  • Architect and manage the Constraint Manager (CM) hierarchy in Cadence Allegro, defining the source of truth for high-speed routing rules and electrical constraints
  • Develop automation scripts (SKILL, Python, or TCL) to streamline layout tasks, DRC checks, and reporting
  • Execute layout for ultra-high-speed interfaces including PCIe Gen5/6, CXL, and custom die-to-die (D2D) interconnects
  • Partner with Power Engineers on PDN strategy, including multi-phase VRM layouts and decoupling capacitor placement...