Sr. Staff/Principal Engineer, Digital Design (San Diego)

About InnoPhase IoT If you are keen to work with a bunch of brilliant people with various backgrounds, if you share the same value of working smart and celebrating successes, if you have enthusiasm for big technology in a small company, if your goals are to learn and experience different aspects of work--not just singing the same song every day, you’ll find your playground at Innophase IoT. We are looking for people seeking AWESOMENESS! If you’re good at what you do, you can work anywhere. If you’re the best at what you do, come work at Innophase IoT!As a Sr. Staff/ Principal Digital Design Engineer, you will be working with a team of design engineers to develop novel SoC products for connectivity and communications. You will also be a key contributor to product definition and resulting detailed device performance and functional requirements specifications. In addition to delivering high quality digital solutions in the context of the product architecture, the team supports other disciplines with work product such as Verilog stimulus files, test benches for device bring up/characterization, test vectors for product manufacturing, etc. Key Responsibilities Contribute to/review SoC specifications and architectures Front to back digital design and verification – RTL through physical implementation Hands on technical leadership Support schedule and resource planning Help define and socialize digital/system design, implementation methodologies and test strategies and flows Debug designs and provide timely closure Work with System, Software, RF, Analog, and Test teams and provide necessary support Job Requirements MS/PhD EE/CS preferred 10 or more years of experience digital SoC development required Experience bringing highly integrated mixed signal SoCs to commercial mass production Experience with embedded systems, wireless protocols, power management, signal processing and standard digital interfaces Deep RTL design knowledge (Verilog/VHDL) and SystemVerilog, checkers, and other design verification techniques Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers) Proven knowledge of synthesis, static timing, DFT and (Front to Back) F2B digital SoC design flow Experience with ATPG, fault grading, scan, BIST, DFT/DFM Proven knowledge of SystemVerilog assertions, Knowledge of languages such as C/C++, Perl, Tcl and Python Strong communication and presentation skills Good skills and interest in mentorship Ability to foresee issues and design in flexibility and workarounds for both known and unknown unknowns Expert in RTL design and implementation (architecture and micro-architecture) Deep knowledge of front-end tools and flow - Verilog simulators, linters, synthesis, static timing, clock trees, power simulation, floor plan development, and power supply implementation Deep knowledge of system modeling and verification using System Verilog or System C Proven knowledge in acquiring and integrating 3rd party IP Hig...