Staff Analog Design Engineer
About Analog DevicesAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X. Staff Analog Design Engineer, Data Center & Energy, IVR Technology About the Role As a Staff Analog Design Engineer at Analog Devices, you will lead the design and development of complex analog and mixed-signal integrated circuits, working with significant latitude to solve challenging technical problems. You'll provide technical leadership on critical projects, contribute to architectural decisions, and mentor less experienced engineers while collaborating with cross-functional teams. This role requires deep technical expertise combined with broader business understanding to drive innovation and ensure successful product delivery across multiple applications and markets. Role OverviewTo expand the team in Munich we are seeking an experienced Analog Design Engineer to contribute to the development of high-performance power management ICs in advanced CMOS nodes. In this role, you will collaborate closely with a team of circuit designers to deliver high-density, ultra efficient circuit implementations that meet aggressive performance and size targets.The ideal candidate has 10+ years of hands-on experience in analog IC design (or 5+ years’ experience in Power IC and DC/DC design), deep expertise in custom IC development flows from definition to layout and silicon evaluation, and thrives in a startup-like, high-accountability culture.Key ResponsibilitiesLeadtechnicalfeasibilityofinnovativearchitecturesforIPmacro-blockswithinPowerICs,i.e.power-stages, gate drivers and various sub-systems (control, diagnostics, monitoring, telemetry, voltage/current/timing references, internal supplies, etc). Explore, compare and derive KPIs and achievable specs for various architectural and process technology options by means of mathematical/prediction models, circuit models, existing designs and/or lab evaluation data.Hands-on custom design of analogue/mixed-signal IP macro-blocks in planar and FinFET technologies. Lead and own design, pre- and post-layout verification (block- and top-level), spec compliance matrix, behavioural modelling, layout implementation, and documentation.Provide guidance, reviews and CAPA to IP-level floorplan and layout implementation of analogue/mixed-signal blocks, with attention to matching, shielding, routing, parasitic, electromigration, DFM, area optimization, etc.Run layout parasitic ex...